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83111hkim 20101027-s00001 no.a1869-1/26 ver.1.00a LC87F2W48A overview the sanyo LC87F2W48A is an 8-bit microcomputer that, centered around a cpu running at a minimum bus cycle time of 83.3ns, integrates on a single chip a number of hardware features such as 50k-byte flash rom (on-board- programmable), 1536-byte ram, an on-chip-debugger, sophisticated 16-bit timers/counters (may be divided into 8-bit timers), a 16-bit timer/counter (may be divided into 8-bit timers/counters or 8-bit pwms), four 8-bit timers with a prescaler, a base timer serving as a time-of-day clock, a high-speed clock counter, a synchronous sio interface, an asynchronous/synchr onous sio interface, a uart interf ace (full duplex), tw o 12-bit pwm channels, a 14-channel ad converter with 12-/8-bit reso lution selector, a system clock frequency divide r, an infrared remote controller receiver circuit, and a 24-source 10-vector interrupt feature. features ? flash rom ? capable of on-board-programming with wide range, 2.7 to 5.5v, of voltage source. ? block-erasable in 128 byte units ? writable in 2-byte units ? 51200 8 bits ? ram ? 1536 9 bits ? minimum bus cycle ? 83.3ns (12mhz) v dd =2.7v to 5.5v note: the bus cycle time here refers to the rom read speed. ordering number : ena1869a cmos ic 50k-byte from and 1536-byte ram integrated 8-bit 1-chip microcontroller * this product is licensed from silicon storage te chnology, inc. (usa), and manufactured and sold by sanyo semiconductor co., ltd. specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer ' s products or equipment. to verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer ' s products or equipment. any and all sanyo semiconductor co.,ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment. the products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appli ances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliab ility and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. if you should intend to use our products for new introduction or other application different from current conditions on the usage of automotive device, communication device, office equipment, industrial equipment etc. , please consult with us about usage condition (temperature, operation time etc.) prior to the intended use. if there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use.
LC87F2W48A no.a1869-2/26 ? minimum instruction cycle time ? 250ns (12mhz) v dd =2.7 to 5.5v ? ports ? normal withstand voltage i/o ports ports i/o direction can be designated in 1-bit units 38 (p0n, p1n, p2n, p31 to p36, p70 to p73, pwm0, pwm1, xt2, cf2) ? dedicated oscillator ports/input ports 2 (xt1, cf1) ? reset pin 1 (res ) ? on-chip debugger pin 1 (owp0) ? power pins 6 (v ss 1 to 3, v dd 1 to 3) ? timers ? timer 0: 16 bit timer / counter with capture register mode 0: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) 2 channels mode 1: 8-bit timer with an 8-bit programmab le prescaler (with an 8-bit capture register) + 8-bit counter (with an 8-bit capture register) mode 2: 16-bit timer with an 8-bit programma ble prescaler (with a 16-bit capture register) mode 3: 16-bit counter (with a 16-bit capture register) ? timer 1: 16-bit timer/counter that supports pwm/toggle outputs mode 0: 8-bit timer with an 8-b it prescaler (with toggle outputs) + 8-bit timer/counter with an 8- bit prescaler (with toggle outputs) mode 1: 8-bit pwm with an 8-bit prescaler 2 channels mode 2: 16-bit timer/counter with an 8-bit prescaler (with toggle outputs) (toggle outputs also possible from the lower-order 8 bits) mode 3: 16-bit timer with an 8-bit prescaler (with toggle outputs) (the lower-order 8 bits can be used as pwm.) ? timer 4: 8-bit timer with a 6-bit prescaler ? timer 5: 8-bit timer with a 6-bit prescaler ? timer 6: 8-bit timer with a 6-bit prescaler (with toggle output) ? timer 7: 8-bit timer with a 6-bit prescaler (with toggle output) ? base timer (1) the clock is selectable from the subclock (32.768khz crystal oscillation), system clock, and timer 0 prescaler output. (2) interrupts are programmable in 5 different time schemes ? high-speed clock counter 1) can count clocks with a maximum clock rate of 20mhz (at a main clock of 10mhz). 2) can generate output real-time. ? serial interface ? sio 0: 8-bit synchronous serial interface (1) lsb first/msb first mode selectable (2) built-in 8-bit baudrate generator (maximum transfer clock cycle=4/3 tcyc) (3) automatic continuous data transmission (1 to 256 bits, specifiable in 1-bit units, suspension and resumption of data transmission possible in 1-byte units) ? sio 1: 8-bit asynchronous / synchronous serial interface mode 0: synchronous 8-bit serial i/o (2- or 3-wire configuration, 2 to 512 tcyc transfer clocks) mode 1: asynchronous serial i/o (half-duplex, 8-data bits, 1-stop bit, 8 to 2048 tcyc baudrates) mode 2: bus mode 1 (start bit, 8-data bits, 2 to 512 tcyc transfer clocks) mode 3: bus mode 2 (start detect, 8-data bits, stop detect)
LC87F2W48A no.a1869-3/26 ? uart ? full duplex ? 7/8/9 bit data bits selectable ? 1 stop bit (2-bit in continuous data transmission) ? built-in baudrate generator ? ad converter: 12 bits/8 bits 14 channels ? 12 bits/8 bits ad converter resolution selectable ? pwm: multifrequency 12-bit pwm 2 channels ? infrared remote controller receiver circuit 1) noise rejection function (noise filter time constant: approx. 120 s when the 32.768khz crystal oscillator is selected as the reference clock source) 2) supports data encording systems such as ppm (pulse position modulation) and manchester encording 3) x?tal hold mode release function ? clock output function ? can generate clock outputs with a frequency of 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 of the source clock selected as the system clock. ? can generate the source clock for the subclock. ? watchdog timer ? external rc watchdog timer ? interrupt and reset signals selectable ? interrupts ? 24 sources, 10 vector addresses 1) provides three levels (low (l), high (h), and highest (x )) of multiplex interrupt control. any interrupt requests of the level equal to or lower than the current interrupt are not accepted. 2) when interrupt requests to two or more vector addresses occur at the same time, the interrupt of the highest level takes precedence over the other interrupts. for interrupts of the same level, the interrupt into the smallest vector address takes precedence. no. vector address level interrupt source 1 00003h x or l int0 2 0000bh x or l int1 3 00013h h or l int2/t0l/int4/remorec2 4 0001bh h or l int3/int5/bt0/bt1 5 00023h h or l t0h 6 0002bh h or l t1l/t1h 7 00033h h or l sio0/uart1 receive 8 0003bh h or l sio1/uart transmit 9 00043h h or l adc/t6/t7 10 0004bh h or l port 0/t4/t5/pwm0,1 ? priority levels x > h > l ? of interrupts of the same level, the one with the smallest vector address takes precedence. ? iflg (list of interrupt source flag function) (1) shows a list of interrupt source flags that cause d a branching to a particular vector address (shown in the table above.) ? subroutine stack levels: 768 levels (the stack is allocated in ram.) ? high-speed multiplication/division instructions ? 16 bits 8 bits (5 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time) ? 16 bits 8 bits (8 tcyc execution time) ? 24 bits 16 bits (12 tcyc execution time)
LC87F2W48A no.a1869-4/26 ? oscillation circuits ? internal oscillation circuits 1) low-speed rc oscillation circuit: for system clock (100khz) 2) medium-speed rc oscillation circuit: for system clock (1mhz) 3) frequency variable rc oscillation circuit: for system clock (6 to 10mhz) (1) adjustable in 0.5% (typ) step from a selected center frequency. (2) measures oscillation clock using a i nput signal from xt1 as a reference. ? external oscillation circuits 1) low speed crystal oscillation circuit: for lo w-speed system clock, with internal rf 2) hi-speed cf oscillation circuit: for system clock, with internal rf (1) both the cf and crystal oscillator circuits stop operation on a system reset. ? system clock divider function ? can run on low current. ? the minimum instruction cycle sel ectable from 300ns, 600ns, 1.2 s, 2.4 s, 4.8 s, 9.6 s, 19.2 s, 38.4 s, and 76.8 s (at a main clock rate of 10mhz). ? standby function ? halt mode: halts instruction execution while allowing the peripheral circuits to continue operation. 1) oscillation is not halted automatically. 2) there are three ways of resetting the halt mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer (3) occurrence of an interrupt ? hold mode: suspends instruction execution and the operation of the peripheral circuits. 1) the cf, rc, and crystal oscilla tors automatically stop operation. 2) there are four ways of resetting the hold mode. (1) setting the reset pin to the low level. (2) system resetting by watchdog timer (3) having an interrupt source established at either int0, int1, int2, int4, or int5 * int0 and int1 hold mode reset is available only when level detection is set. (4) having an interrupt source established at port 0 ? x'tal hold mode: suspends instruction execution and the oper ation of the peripheral circ uits except base timer and infrared remote controller receiver circuit. 1) the cf and rc oscillators automatically stop operation. 2) the state of crystal oscillation established wh en the x'tal hold mode is entered is retained. 3) there are six ways of resetting the x'tal hold mode. (1) setting the reset pin to the low level (2) system resetting by watchdog timer (3) having an interrupt source established at either int0, int1, int2, int4, or int5 * int0 and int1 x'tal hold mode reset is av ailable only when level detection is set. (4) having an interrupt source established at port 0 (5) having an interrupt source established in the base timer circuit (6) having an interrupt source established in the infrared remote controller receiver circuit ? onchip debugger ? supports software debugging with the ic mounted on the target board. ? data security function (flash versions only) ? protects the program data stored in flash memory from unauthorized read or copy. note: this data security function does not necessarily provide absolute data security.
LC87F2W48A no.a1869-5/26 ? package form ? sqfp48 (7 7) (lead-/halogen-free type) ? development tools ? on-chip-debugger: tcb87-typec (1 wire version) + LC87F2W48A ? flash rom programming boards package programming boards sqfp48 (7 7) w87f55256sq package dimensions unit : mm (typ) 3163b sanyo : sqfp48(7x7) 7.0 7.0 9.0 9.0 0.15 0.5 (1.5) 0.1 1.7max 0.18 0.5 (0.75) 112 13 24 25 36 37 48
LC87F2W48A no.a1869-6/26 pin assignment sanyo: sqip48 (77) ?l ead-/halogen-free type? sqfp name sqfp name sqfp name 1 p73/int3/t0in/rmin 17 pwm1 33 p24/int5/t1in 2 res 18 pwm0 34 p25/int5/t1in 3 xt1/an10 19 v dd 2 35 p26/int5/t1in 4 xt2/an11 20 v ss 2 36 p27/int5/t1in 5 v ss 1 21 p00/an0 37 p36 6 cf1/an12 22 p01/an1 38 p35 7 cf2/an13 23 p02/an2 39 v dd 3 8 v dd 1 24 p03/an3 40 v ss 3 9 p10/so0 25 p04/an4 41 p34 10 p11/si0/sb0 26 p05/cko/an5 42 p33 11 p12/sck0 27 p06/t6o/an6 43 p32 12 p13/so1 28 p07/t7o/an7 44 p31 13 p14/si1/sb1 29 p20/utx/int4/t1in 45 owp0 14 p15/sck1 30 p21/urx/int4 /t1in 46 p70/int0/t0lcp/an8 15 p16/t1pwml 31 p22/int4/t1in 47 p71/int1/t0hcp/an9 16 p17/t1pwmh/buz 32 p23/int4/t1in 48 p72/int2/t0in lc87f2w48 a to p view p27/int5/t1in p26/int5/t1in p25/int5/t1in p24/int5/t1in p23/int4/t1in p22/int4/t1in p21/urx/int4/t1in p20/utx/int4/t1in p07/t7o/an7 p06/t6o/an6 p05/cko/an5 p04/an4 p36 p35 v dd 3 v ss 3 p34 p33 p32 p31 owp0 p70/int0/t0lcp/an8 p71/int1/t0hcp/an9 p72/int2/t0in p73/int3/t0in/rmin res xt1/an10 xt2/an11 v ss 1 cf1/an12 cf2/an13 v dd 1 p10/so0 p11/si0/sb0 p12/sck0 p13/so1 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 37 38 39 40 41 42 43 44 45 46 47 48 p03/an3 p02/an2 p01/an1 p00/an0 v ss 2 v dd 2 pwm0 pwm1 p17/t1pwmh/buz p16/t1pwml p15/sck1 p14/si1/sb1 24 23 22 21 20 19 18 17 16 15 14 13
LC87F2W48A no.a1869-7/26 system block diagram interrupt control standby control ir pla bus interface port 0 port 1 sio0 sio1 timer 0 timer 1 timer 4 timer 5 port 3 port 7 adc alu flash rom pc acc b register c register psw rar ram stack pointer watchdog timer pwm0/1 uart1 base timer timer 6 int0-2, int4, 5 int3 (noise filter) timer 7 on-chip debugger port 2 i nfrared remote controller receiver circuit reset control wdt res clock generator cf vmrc x?tal medium- speed rc low- speed rc
LC87F2W48A no.a1869-8/26 pin description pin name i/o description option v ss 1 to v ss 3 - - power supply pins no v dd 1 to v dd 3 - + power supply pin no port 0 p00 to p07 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? hold reset input ? port 0 interrupt input ? pin functions p05: system clock output p06: timer 6 toggle output p07: timer 7 toggle output p00(an0) to p07(an7): ad converter input yes port 1 p10 to p17 i/o ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p10: sio0 data output p11: sio0 data input/bus i/o p12: sio0 clock i/o p13: sio1 data output p14: sio1 data input/bus i/o p15: sio1 clock i/o p16: timer 1pwml output p17: timer 1pwmh output/beeper output yes port 2 ? 8-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p20: uart transmit p21: uart receive p20 to p23: int4 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input p24 to p27: int5 input/hold reset input/timer 1 event in put/timer 0l capture input/ timer 0h capture input ? interrupt acknowledge type rising falling rising & falling h level l level int4 int5 enable enable enable enable enable enable disable disable disable disable p20 to p27 i/o yes port 3 p31 to p36 i/o ? 6-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. yes continued on next page.
LC87F2W48A no.a1869-9/26 continued from preceding page. pin name i/o description option port 7 ? 4-bit i/o port ? i/o specifiable in 1-bit units ? pull-up resistors can be turned on and off in 1-bit units. ? pin functions p70: int0 input/hold reset input/time r 0l capture input/watchdog timer output p71: int1 input/hold reset i nput/timer 0h capture input p72: int2 input hold reset input/time r 0 event input/timer 0l capture input p73: int3 input (with noise filter)/time r 0 event input/timer 0h capture input/ infrared remote controller receiver input p70(an8), p71(an9): ad converter input ? interrupt acknowledge type rising falling rising & falling h level l level int0 int1 int2 int3 enable enable enable enable enable enable enable enable disable disable enable enable enable enable disable disable enable enable disable disable p70 to p73 i/o no pwm0 i/o ? pwm0 output port ? general-purpose i/o available no pwm1 i/o ? pwm1 output port ? general-purpose i/o available no res i/o external reset input/internal reset output no xt1 input ? 32.768khz crystal oscillator input pin ? shared pins general-purpose input port ad converter input port: an10 no xt2 i/o ? 32.768khz crystal oscillator output pin ? shared pins general-purpose i/o port ad converter input port: an11 no cf1 input ? ceramic resonator input pin ? shared pins general-purpose input port ad converter input port: an12 no cf2 i/o ? ceramic resonator output pin ? shared pins general-purpose i/o port ad converter input port: an13 no owp0 i/o on-chip debugger pin no
LC87F2W48A no.a1869-10/26 on-chip debugger pin connection requirements for the treatment of the on-chip debugger pins, refer to the separately available documents entitled ?rd87 on-chip debugger installation manual? recommended unused pin connections port output types the table below lists the types of port outputs and the presence/absence of a pull-up resistor. data can be read into any input port even if it is in the output mode. note 1: the control of the presence or absence of the programmable pull-up resistors for port 0 and the switching between low- and high-impedance pull-up connection is exercised in 1-bit units. recommended unused pin connections port name board software p00 to p07 open output low p10 to p17 open output low p20 to p27 open output low p31 to p36 open output low p70 to p73 open output low pwm0, pwm1 open output low xt1 pulled low with a 100k resistor or less general-purpose input port xt2 open output low cf1 pulled low with a 100k resistor or less general-purpose input port cf2 open output low port name option selected in units of option type output type pull-up resistor 1 cmos programmable (note 1) p00 to p07 1 bit 2 nch-open drain programmable (note 1) 1 cmos programmable p10 to p17 1 bit 2 nch-open drain programmable 1 cmos programmable p20 to p27 1 bit 2 nch-open drain programmable 1 cmos programmable p31 to p36 1 bit 2 nch-open drain programmable p70 - no nch-open drain programmable p71 to p73 - no cmos programmable pwm0, pwm1 - no cmos no xt1 - no input for 32.768khz crystal oscillator (input only) no xt2 - no output for 32.768khz crystal oscillator (nch-open drain when in general-purpose output mode) no cf1 - no input for ceramic resonator oscillator (input only) no cf2 - no output for ceramic resonator oscillator (nch-open drain when in general-purpose output mode) no
LC87F2W48A no.a1869-11/26 user option table note: to reduce v dd 1 signal noise and to increase the duration of the backup battery supply, v ss 1, v ss 2, and v ss 3 should connect to each other and they should also be grounded. example 1: during backup in hold mode, port output ?h? level is supplied from the back-up capacitor. example 2: during backup in hold mode, output is not held high and its value in unsettled. option name option to be applied on flash-rom vers ion option selected in units of option selection cmos p00 to p07 { 1 bit nch-open drain cmos p10 to p17 { 1 bit nch-open drain cmos p20 to p27 { 1 bit nch-open drain cmos port output type p31 to p36 { 1 bit nch-open drain 00000h program start address - { - 0fe00h v ss 1 v ss 2 v ss 3 v dd 1 v dd 2 v dd 3 power supply back-up capacitor lsi lsi v dd 1 v dd 2 v dd 3 power supply back-up capacitor v ss 1 v ss 2 v ss 3
LC87F2W48A no.a1869-12/26 absolute maximum ratings at ta=25c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pins conditions v dd [v] min typ max unit maximum supply voltage v dd max v dd 1, v dd 2, v dd 3 v dd 1=v dd 2=v dd 3 -0.3 +6.5 input voltage v i xt1, cf1, res -0.3 v dd +0.3 input/output voltage v io ports 0, 1, 2, 3 port 7 pwm0, pwm1 xt2, cf2 -0.3 v dd +0.3 v ioph(1) ports 0, 1, 2, 3 cmos output selected per 1 applicable pin -10 ioph(2) pwm0, pwm1 per 1 applicable pin -20 peak output current ioph(3) p71 to p73 per 1 applicable pin -5 iomh(1) ports 0, 1, 2, 3 cmos output select per 1 applicable pin -7.5 iomh(2) pwm0, pwm1 per 1 applicable pin -15 mean output current (note 1-1) iomh(3) p71 to p73 per 1 applicable pin -3 ioah(1) p71 to p73 total of all applicable pins -10 ioah(2) port 0 total of all applicable pins -25 ioah(3) port 1 pwm0, pwm1 total of all applicable pins -25 ioah(4) ports 0, 1 pwm0, pwm1 total of all applicable pins -45 ioah(5) port 2 p35, p36 total of all applicable pins -25 ioah(6) p31 to p34 total of all applicable pins -25 high level output current total output current ioah(7) ports 2, 3 total of all applicable pins -45 iopl(1) p02 to p07 ports 1, 2, 3 pwm0, pwm1 per 1 applicable pin 20 iopl(2) p00, p01 per 1 applicable pin 30 peak output current iopl(3) port 7 xt2, cf2 per 1 applicable pin 10 ioml(1) p02 to p07 ports 1, 2, 3 pwm0, pwm1 per 1 applicable pin 15 ioml(2) p00, p01 per 1 applicable pin 20 mean output current (note 1-1) ioml(3) port 7 xt2, cf2 per 1 applicable pin 7.5 ioal(1) port 7 xt2, cf2 total of all applicable pins 15 ioal(2) port 0 total of all applicable pins 45 ioal(3) port 1 pwm0, pwm1 total of all applicable pins 45 ioal(4) ports 0, 1 pwm0, pwm1 total of all applicable pins 80 ioal(5) port 2 p35, p36 total of all applicable pins 45 ioal(6) p31 to p34 total of all applicable pins 45 low level output current total output current ioal(7) ports 2, 3 total of all applicable pins 60 ma pdmax(1) ta=-40 to +85c package only 129 power dissipation pdmax(2) sqfp48(77) ta=-40 to +85c package with thermal resistance board (note 1-2) 383 mw operating temperature range topr -40 85 storage temperature range tstg -55 125 c note 1-1: the mean output current is a mean value measured over 100ms. note 1-2: semi standards thermal resistance board (s ize: 76.1114.31.6 tmm, glass epoxy) is used.
LC87F2W48A no.a1869-13/26 allowable operating conditions at ta=-40 to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit operating supply voltage v dd v dd 1=v dd 2=v dd 3 0.245 s tcyc 200 s 2.7 5.5 memory sustaining supply voltage vhd v dd 1=v dd 2=v dd 3 ram and register contents sustained in hold mode. 2.0 5.5 v ih (1) ports 1, 2, 3 p71 to p73 p70 port input/ interrupt side pwm0, pwm1 2.7 to 5.5 0.3v dd +0.7 v dd v ih (2) port 0 2.7 to 5.5 0.3v dd +0.7 v dd v ih (3) port 70 watchdog timer side 2.7 to 5.5 0.9v dd v dd high level input voltage v ih (4) xt1, xt2, cf1, cf2 res 2.7 to 5.5 0.75v dd v dd 4.0 to 5.5 v ss 0.1v dd +0.4 v il (1) ports 1, 2, 3 p71 to p73 p70 port input/ interrupt side pwm0, pwm1 2.7 to 4.0 v ss 0.2v dd 4.0 to 5.5 v ss 0.15v dd +0.4 v il (2) port 0 2.7 to 4.0 v ss 0.2v dd v il (3) port 70 watchdog timer side 2.7 to 5.5 v ss 0.8v dd -1.0 low level input voltage v il (4) xt1, xt2, cf1, cf2 res 2.7 to 5.5 v ss 0.25v dd v instruction cycle time tcyc (note 2-1) 2.7 to 5.5 0.245 200 s cf2 pin open system clock frequency division ratio=1/1 external system clock duty=50 5% 2.7 to 5.5 0.1 12 external system clock frequency fexcf cf1 cf2 pin open system clock frequency division ratio=1/2 external system clock duty=50 5% 3.0 to 5.5 0.2 24.4 fmcf(1) cf1, cf2 12mhz ceramic oscillation see fig. 1. 2.7 to 5.5 12 fmcf(2) cf1, cf2 10mhz ceramic oscillation see fig. 1. 2.7 to 5.5 10 4mhz ceramic oscillation. cf oscillation normal amplifier size selected. (cflamp=0) see fig. 1. 2.7 to 5.5 4 oscillation frequency range (note 2-2) fmcf(3) cf1, cf2 4mhz ceramic oscillation. cf oscillation low amplifier size selected. (cflamp=1) see fig. 1. 2.7 to 5.5 4 mhz note 2-1: relationship between tcyc and oscillation frequency is 3/fmcf at a division ratio of 1/1 and 6/fmcf at a division ratio of 1/2. note 2-2: see tables 1 and 2 for the oscillation constants. continued on next page.
LC87F2W48A no.a1869-14/26 continued from preceding page. specification parameter symbol pin/remarks conditions v dd [v] min typ max unit fmvmrc frequency variable rc oscillation. (vm3frq1/0=0/1) (note 2-3) 2.7 to 5.5 8.0 fmrc internal medium-speed rc oscillation 2.7 to 5.5 0.5 1.0 2.0 mhz fmsrc internal low-speed rc oscillation 2.7 to 5.5 50 100 200 oscillation frequency range (note 2-2) fsx?tal xt1, xt2 32.768khz crystal oscillation see fig. 3. 2.7 to 5.5 32.768 khz frequency variable rc oscillation usable range opvmrc frequency variable rc oscillation. (vm3frq1/0=0/1) 2.7 to 5.5 6 8 10 mhz vmadj(1) each step of v3rchbn 2.7 to 5.5 3.6 7.0 11 vmadj(2) each step of v3fchbn 2.7 to 5.5 0.7 1.5 2.3 frequency variable rc oscillation adjustment range vmadj(3) each step of v3dchn 2.7 to 5.5 0.2 0.5 1.1 % note 2-2: see tables 1 and 2 for the oscillation constants. note 2-3: when switching the system clock, allow an oscillation stabilization time of 100 s or longer after the multifrequency rc oscillator circuit transmits from the "oscillation stopped" to "oscillation enabled" state.
LC87F2W48A no.a1869-15/26 electrical characteristics at ta=-40 to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit i ih (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 output disabled pull-up resistor off v in =v dd (including output tr's off leakage current) 2.7 to 5.5 1 i ih (2) xt1, xt2, cf2 input port selected v in =v dd 2.7 to 5.5 1 high level input current i ih (3) cf1 v in =v dd 2.7 to 5.5 15 i il (1) ports 0, 1, 2, 3 port 7 res pwm0, pwm1 output disabled pull-up resistor off v in =v ss (including output tr's off leakage current) 2.7 to 5.5 -1 i il (2) xt1, xt2, cf2 input port selected v in =v ss 2.7 to 5.5 -1 low level input current i il (3) cf1 v in =v ss 2.7 to 5.5 -15 a v oh (1) i oh =-1ma 4.5 to 5.5 v dd -1 v oh (2) ports 0, 1, 2, 3 p71 to p73 i oh =-0.35ma 2.7 to 5.5 v dd -0.4 v oh (3) i oh =-6ma 4.5 to 5.5 v dd -1 high level output voltage v oh (4) pwm0, pwm1 p05(system clock output function used) i oh =-1.4ma 2.7 to 5.5 v dd -0.4 v ol (1) i ol =10ma 4.5 to 5.5 1.5 v ol (2) ports 0, 1, 2, 3 pwm0, pwm1 i ol =1.4ma 2.7 to 5.5 0.4 v ol (3) i ol =25ma 4.5 to 5.5 1.5 v ol (4) p00, p01 i ol =4ma 2.7 to 5.5 0.4 low level output voltage v ol (5) port 7, xt2, cf2 i ol =1.4ma 2.7 to 5.5 0.4 v rpu(1) 4.5 to 5.5 15 35 80 rpu(2) ports 0, 1, 2, 3 port 7 v oh =0.9v dd when port 0 selected low-impedance pull-up. 2.7 to 5.5 18 50 230 pull-up resistance rpu(3) port 0 v oh =0.9v dd when port 0 selected high-impedance pull-up. 2.7 to 5.5 100 210 400 k hysteresis voltage vhys ports 1, 2, 3, 7 res , xt2 2.7 to 5.5 0.1v dd v pin capacitance cp all pins for pins other than that under test: v in =v ss , f=1mhz, ta=25 c 2.7 to 5.5 10 pf
LC87F2W48A no.a1869-16/26 serial i/o characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v 1. sio0 serial i/o characteristics (note 4-1-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(1) 2 low level pulse width tsckl(1) 1 tsckh(1) see fig. 6. 1 input clock high level pulse width tsckha(1) sck0(p12) continuous data transmission/ reception mode see fig. 6. (note 4-1-2) 2.7 to 5.5 4 frequency tsck(2) 4/3 tcyc low level pulse width tsckl(2) 1/2 tsckh(2) cmos output selected see fig. 6 1/2 tsck serial clock output clock high level pulse width tsckha(2) sck0(p12) continuous data transmission/ reception mode cmos output selected. see fig. 6. 2.7 to 5.5 tsckh(2) +2tcyc tsckh(2) +(10/3) tcyc tcyc data setup time tsdi(1) 0.05 serial input data hold time thdi(1) sb0(p11), si0(p11) must be specified with respect to rising edge of sioclk. see fig. 6. 2.7 to 5.5 0.05 tdd0(1) continuous data transmission/reception mode (note 4-1-3) (1/3)tcyc +0.08 input clock tdd0(2) synchronous 8-bit mode (note 4-1-3) 1tcyc +0.08 serial output output clock output delay time tdd0(3) so0(p10), sb0(p11) (note 4-1-3) 2.7 to 5.5 (1/3)tcyc +0.08 s note 4-1-1: these specifications are theoretical values. add margin depending on its use. note 4-1-2: when using the serial clock input in the con tinuous data transmission/recep tion mode, make sure, at the beginning of continuous data transmission/reception, th at the interval from the time si0run is set while the serial clock is high till the first falling edge of the serial clock is longer than tsckha. note 4-1-3: must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6.
LC87F2W48A no.a1869-17/26 2. sio1 serial i/o characteristics (note 4-2-1) specification parameter symbol pin/remarks conditions v dd [v] min typ max unit frequency tsck(3) 2 low level pulse width tsckl(3) 1 input clock high level pulse width tsckh(3) sck1(p15) see fig. 6. 2.7 to 5.5 1 frequency tsck(4) 2 tcyc low level pulse width tsckl(4) 1/2 serial clock output clock high level pulse width tsckh(4) sck1(p15) cmos output selected see fig. 6. 2.7 to 5.5 1/2 tsck data setup time tsdi(2) 0.05 serial input data hold time thdi(2) sb1(p14), si1(p14) must be specified with respect to rising edge of sioclk. see fig. 6. 2.7 to 5.5 0.05 serial output output delay time tdd0(4) so1(p13), sb1(p14) must be specified with respect to falling edge of sioclk. must be specified as the time to the beginning of output state change in open drain output mode. see fig. 6. 2.7 to 5.5 (1/3)tcyc +0.08 s note 4-2-1: these specifications are theoretical values. add margin depending on its use. pulse input conditions at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions vdd[v] min typ max unit tpih(1) tpil(1) int0(p70), int1(p71), int2(p72), int4(p20 to p23), int5(p24 to p27) interrupt source flag can be set. event inputs for timer 0 or 1 are enabled. 2.7 to 5.5 1 tpih(2) tpil(2) int3(p73) when noise filter time constant is 1/1 interrupt source flag can be set. event inputs for timer 0 are enabled. 2.7 to 5.5 2 tpih(3) tpil(3) int3(p73) when noise filter time constant is 1/32 interrupt source flag can be set. event inputs for timer 0 are enabled. 2.7 to 5.5 64 tpih(4) tpil(4) int3(p73) when noise filter time constant is 1/128 interrupt source flag can be set. event inputs for timer 0 are enabled. 2.7 to 5.5 256 tcyc tpih(5) tpil(5) rmin(p73) recognized by the infrared remote controller receiver circuit as a signal. 2.7 to 5.5 4 rmck (note 5-1) high/low level pulse width tpil(6) res resetting is enabled. 2.7 to 5.5 200 s note 5-1: represents the period of the reference clock (1 to 128 tcyc or the source frequen cy of the subclock) for the infrared remote controller receiver circuit.
LC87F2W48A no.a1869-18/26 ad converter characteristics at v ss 1 = v ss 2 = v ss 3 = 0v <12bits ad converter mode at ta = -40 to +85 c> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 2.7 to 5.5 12 bit (note 6-1) 3.0 to 5.5 16 absolute accuracy et (note 6-1) 2.7 to 3.6 20 lsb 4.5 to 5.5 32 115 see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 64 115 conversion time tcad see conversion time calculation formulas. (note 6-2) 2.7 to 3.6 410 425 s analog input voltage range vain an0(p00) to an7(p07), an8(p70), an9(p71), an10(xt1), an11(xt2), an12(cf1), an13(cf2) 2.7 to 5.5 v ss v dd v iainh(1) vain=v dd 2.7 to 5.5 1 iainl(1) analog channel except an12 vain=v ss 2.7 to 5.5 -1 iainh(2) vain=v dd 2.7 to 5.5 15 analog port input current iainl(2) an12 vain=v ss 2.7 to 5.5 -15 a <8bits ad converter mode at ta = -40 to +85 c> specification parameter symbol pin/remarks conditions v dd [v] min typ max unit resolution n 2.7 to 5.5 8 bit absolute accuracy et (note 6-1) 2.7 to 5.5 1.5 lsb 4.5 to 5.5 20 70 see conversion time calculation formulas. (note 6-2) 3.0 to 5.5 40 70 conversion time tcad see conversion time calculation formulas. (note 6-2) 2.7 to 3.6 250 265 s analog input voltage range vain an0(p00) to an7(p07), an8(p70), an9(p71), an10(xt1), an11(xt2), an12(cf1), an13(cf2) 2.7 to 5.5 v ss v dd v iainh(1) vain=v dd 2.7 to 5.5 1 iainl(1) analog channel except an12 vain=v ss 2.7 to 5.5 -1 iainh(2) vain=v dd 2.7 to 5.5 15 analog port input current iainl(2) an12 vain=v ss 2.7 to 5.5 -15 a conversion time calculation formulas: 12bits ad converter mode: tcad(conversion time)= ((52/(ad division ratio))+2)(1/3)tcyc 8bits ad converter mode: tcad(conversion time)=((32/(ad division ratio))+2)(1/3)tcyc ad conversion time (tcad) external oscillation (fmcf) operating supply voltage range (v dd ) system division ratio (sysdiv) cycle time (tcyc) ad division ratio (addiv) 12bit ad 8bit ad 4.5v to 5.5v 1/1 250ns 1/8 34.8 s 21.5 s cf-12mhz 3.0v to 5.5v 1/1 250ns 1/16 69.5 s 42.8 s 4.5v to 5.5v 1/1 300ns 1/8 41.8 s 25.8 s cf-10mhz 3.0v to 5.5v 1/1 300ns 1/16 83.4 s 51.4 s 3.0v to 5.5v 1/1 750ns 1/8 104.5 s 64.5 s cf-4mhz 2.7v to 3.6v 1/1 750ns 1/32 416.5 s 256.5 s note 6-1: the quantization error ( 1/2lsb) must be excluded from the absolute accuracy. the absolute accuracy must be measured in the microcontroller's state in which no i/o operations occur at the pins adjacent to the analog input channel. note 6-2: the conversion time refers to the period from the time an instruction for starting a conversion process till the time the conversion results register(s) are loaded with a complete digital conversion value corresponding to the analog input value. the conversion time is 2 times the normal-time conversion time when: ? the first ad conversion is performed in the 12-bit ad conversion mode after a system reset. ? the first ad conversion is performed after the ad conversion mode is switched from 8-bit to 12-bit conversion mode.
LC87F2W48A no.a1869-19/26 consumption current characteristics at ta = -40 c to +85 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 2.7 to 5.5 4.5 9.5 iddop(1) ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 2.7 6.5 3.0 to 5.5 5 10.5 iddop(2) ? cf1=24mhz external clock ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to cf1 side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 3.0 to 3.6 3 7.2 2.7 to 5.5 4 8.2 iddop(3) ? fmcf=10mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 10mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 2.4 5.8 2.7 to 5.5 2 4.3 iddop(4) ? fmcf=4mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 4mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 1.3 3 2.7 to 5.5 0.8 2.1 iddop(5) ? cf oscillation low amplifier size selected. (cflamp=1) ? fmcf=4mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 4mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/4 frequency division ratio 2.7 to 3.6 0.5 1.2 2.7 to 5.5 0.5 1.8 iddop(6) ? external fmcf oscillation stopped. ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to internal medium speed rc oscillation. ? internal low speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 0.3 0.95 2.7 to 5.5 3.5 6.8 iddop(7) ? external fmcf oscillation stopped. ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 8mhz with frequency variable rc oscillation ? internal low speed and medium speed rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 2.3 5.2 ma 2.7 to 5.5 58 200 normal mode consumption current (note 7-1) iddop(8) v dd 1 =v dd 2 =v dd 3 ? external fsx?tal and fmcf oscillation stopped. ? system clock set to internal low speed rc oscillation. ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 37 135 a note 7-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. continued on next page.
LC87F2W48A no.a1869-20/26 continued from preceding page. specification parameter symbol pin/ remarks conditions v dd [v] min typ max unit 2.7 to 5.5 38 130 normal mode consumption current (note 7-1) iddop(9) v dd 1 = v dd 2 = v dd 3 ? external fmcf oscillation stopped. ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768khz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 12 65 a 2.7 to 5.5 2 3.1 iddhalt(1) halt mode ? fmcf=12mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 12mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 0.9 1.7 3.0 to 5.5 2.2 3.5 iddhalt(2) halt mode ? cf1=24mhz external clock ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to cf1 side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 3.0 to 3.6 1 2 2.7 to 5.5 1.8 2.8 iddhalt(3) halt mode ? fmcf=10mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 10mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 0.8 1.5 2.7 to 5.5 1 1.6 iddhalt(4) halt mode ? fmcf=4mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 4mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 0.4 0.8 2.7 to 5.5 0.5 1 iddhalt(5) halt mode ? cf oscillation low amp lifier size selected. (cflamp=1) ? fmcf=4mhz ceramic oscillation mode ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 4mhz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/4 frequency division ratio 2.7 to 3.6 0.2 0.5 2.7 to 5.5 0.35 0.8 halt mode consumption current (note 7-1) iddhalt(6) v dd 1 = v dd 2 = v dd 3 halt mode ? external fmcf oscillation stopped. ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to internal medium speed rc oscillation ? internal low speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 0.15 0.4 ma note 7-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. continued on next page.
LC87F2W48A no.a1869-21/26 continued from preceding page specification parameter symbol pin/ remarks conditions v dd [v] min. typ. max. unit 2.7 to 5.5 1.5 2.4 iddhalt(7) halt mode ? external fmcf oscillation stopped. ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 8mhz with frequency variable rc oscillation ? internal low speed and medium speed rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 1 1.6 ma 2.7 to 5.5 18 74 iddhalt(8) halt mode ? external fsx?tal and fmcf oscillation stopped. ? system clock set to internal low speed rc oscillation. ? internal medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/1 frequency division ratio 2.7 to 3.6 9 40 2.7 to 5.5 27 95 halt mode consumption current (note 7-1) iddhalt(9) v dd 1 = v dd 2 = v dd 3 halt mode ? external fmcf oscillation stopped. ? fsx?tal=32.768khz crystal oscillation mode ? system clock set to 32.768 khz side ? internal low speed and medium speed rc oscillation stopped. ? frequency variable rc oscillation stopped. ? 1/2 frequency division ratio 2.7 to 3.6 5.5 42 a 2.7 to 5.5 0.04 20 hold mode consumption current (note 7-1) iddhold(1) hold mode ? cf1=v dd or open (external clock mode) 2.7 to 3.6 0.03 10 2.7 to 5.5 25 88 timer hold mode consumption current (note 7-1) iddhold(2) v dd 1 = v dd 2 = v dd 3 timer hold mode ? cf1=vdd or open (external clock mode) ? fsx?tal=32.768khz crystal oscillation mode 2.7 to 3.6 4.5 38 a note 7-1: values of the consumption current do not include current that flows into the output transistors and internal pull-up resistors. f-rom programming characteristics at ta = +10 c to +55 c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit onboard programming current iddfw v dd 1 = v dd 2 = v dd 3 only current of the flash block. 2.7 to 5.5 5 10 ma tfw(1) erasing time 20 30 ms programming time tfw(2) programming time 2.7 to 5.5 40 60 s
LC87F2W48A no.a1869-22/26 uart (full duplex) operating conditions at ta = -40c to +85c, v ss 1 = v ss 2 = v ss 3 = 0v specification parameter symbol pin/remarks conditions v dd [v] min typ max unit transfer rate ubr utx(p20), urx(p21) 2.7 to 5.5 16/3 8192/3 tcyc data length: 7, 8, and 9 bits (lsb first) stop bits: 1 bit (2-bit in continuous data transmission) parity bits: none example of continuous 8-bit data transmission mode processing (first transmit data=55h) example of continuous 8-bit da ta reception mode processing (first receive data=55h) characteristics of a sample main system clock oscillation circuit given below are the characteristics of a sample main syst em clock oscillation circuit that are measured using a sanyo-designated oscillation characteristics evaluation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 1 characteristics of a sample main system clock oscillator circuit with a ceramic oscillator ? cf oscillation normal amplifier size selected (cflamp=0) circuit constant oscillation stabilization time (symbol: tmscf) nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks 12mhz cstce12m0g52-r0 (10) (10) open 680 2.7 to 5.5 0.03 cstce10m0g52-r0 (10) (10) open 680 2.7 to 5.5 0.03 10mhz cstls10m0g53-b0 (15) (15) open 680 2.7 to 5.5 0.03 cstce8m00g52-r0 (10) (10) open 1.0k 2.7 to 5.5 0.03 8mhz cstls8m00g53-b0 (15) (15) open 1.0k 2.7 to 5.5 0.03 cstcr6m00g53-r0 (15) (15) open 1.5k 2.7 to 5.5 0.05 6mhz cstls6m00g53-b0 (15) (15) open 1.5k 2.7 to 5.5 0.03 cstcr4m00g53-r0 (15) (15) open 1.5k 2.7 to 5.5 0.05 4mhz murata cstls4m00g53-b0 (15) (15) open 1.5k 2.7 to 5.5 0.03 internal c1,c2 transmit data (lsb first) start of transmission end of transmission ubr start bit stop bit stop bit end of reception ubr receive data (lsb first) start of reception start bit
LC87F2W48A no.a1869-23/26 ? cf oscillation low amplifier size selected (cflamp=1) circuit constant oscillation stabilization time (symbol: tmscf) nominal frequency vendor name oscillator name c1 [pf] c2 [pf] rf1 [ ] rd1 [ ] operating voltage range [v] typ [ms] max [ms] remarks cstcr4m00g53-r0 (15) (15) open 1.0k 2.7 to 5.5 0.07 4mhz murata cstls4m00g53-b0 (15) (15) open 1.0k 2.7 to 5.5 0.05 internal c1,c2 the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after an instruction for starting the main clock oscillation circuit or th e time interval that is required for the oscillation to get stabilized (when oscillation is enabled befo re hold or x?tal hold mode is entere d) after that mode is released (see figure 4). characteristics of a sample subs ystem clock oscillator circuit given below are the characteristics of a sample subsystem clock oscillation circuit that are measured using a sanyo- designated oscillation characteristics eval uation board and external components with circuit constant values with which the oscillator vendor confirmed normal and stable oscillation. table 2 characteristics of a sample subsystem cl ock oscillator circuit with a crystal oscillator circuit constant oscillation stabilization time (symbol: tmsxtal) nominal frequency vendor name oscillator name c3 [pf] c4 [pf] rf2 [ ] rd2 [ ] operating voltage range [v] typ [s] max [s] remarks 32.768khz epson toyocom mc-306 18 18 open 560k 2.7 to.5.5 1.5 3.0 applicable cl value= 12.5pf the oscillation stabilization time refers to the time interval th at is required for the oscillation to get stabilized after the instruction for starting the subclock oscillation circuit or the time interval that is required for the oscillation to get stabilized (when oscillation is enabled before hold mode is entered) after that mode is released (see figure 4). note: the components that are involved in oscillation should be placed as close to the ic and to one another as possible because they are vulnerable to the influences of the circuit pattern. figure 1 cf oscillator circuit figure 2 xt oscillator circuit figure 3 ac timing measurement point 0.5v dd cf2 cf1 c3 rd2 c4 x?tal xt2 xt1 rf2 c1 rd1 c2 cf rf1
LC87F2W48A no.a1869-24/26 reset time and oscillation stabilizing time hold release signal and oscillation stabilization time (note: when oscillation is enabled before hold mode is entered.) figure 4 oscillation stabilization times medium-speed rc oscillation or low-speed rc oscillation cf1, cf2 (note) xt1, xt2 ( note ) state hold reset signal hold reset signal absent hold reset signal valid tmscf tmsxtal hold halt power suppl y res medium-s p eed rc oscillation cf1, cf2 xt1, xt2 reset time tmscf tmsxtal o p eratin g mode unpredictable reset instruction execution v dd operating v dd lower limit 0v instruction for enabling oscillation executed
LC87F2W48A no.a1869-25/26 figure 5 reset circuit figure 6 serial input/output wave forms figure 7 pulse input timing signal waveform c res v dd r res res note: determine the value of c res and r res so that the reset signal is present for a period of 200 s after the supply voltage goes beyond the lower limit of the ic?s operating voltage. tpil tpih di0 di7 di2 di3 di4 di5 di6 di8 do0 do7 do2 do3 do4 do5 do6 do8 di1 do1 sioclk: datain: dataout: dataout: datain: sioclk: dataout: datain: sioclk: tsck tsckl tsckh thdi tsdi tddo tsckl tsckha thdi tsdi tddo data ram transfer period (sio0 only) data ram transfer period (sio0 only)
LC87F2W48A no.a1869-26/26 ps this catalog provides information as of august, 2011. specifications and information herein are subject to change without notice. sanyo semiconductor co.,ltd. assumes no responsib ility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all sanyo semiconductor co.,ltd. products described or contained herein. sanyo semiconductor co.,ltd. strives to supply high-quality high-reliab ility pr oducts, however, any and all semiconductor products fail or malfunction with some probab ility. it is possible that these pr obab ilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause dam age to other property. when designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of sanyo semiconductor co.,ltd. or any third party. sanyo semiconductor co.,ltd. shall not be liable for any claim or suits with regard to a third party's intellctual property rights which has resulted from the use of the technical information and products mentioned above. any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. when designing equip ment, refer to the "delivery specification" for the sanyo semiconductor co.,ltd. product that you intend to use. in the event that any or all sanyo semiconductor co.,ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of sanyo semiconductor co.,ltd.

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